Modern telecommunication electronics that utilizes digital radio often uses an I/Q-mixer. I/Q-mixers address the problem of maximizing information transmission in a limited bandwidth by allowing the user to modulate both the in-phase and quadrature components of a carrier simultaneously, doubling the information density.
In order to drive an I/Q mixer a divider able to create 25% duty-cycle signals from a differential externally supplied clock at 2*fLO is often used. Such a divider is disclosed in a conference paper by Ivan Fabiano et al., “SAW-less analog front-end receivers for TDD and FDD”, ISSC2013, p 82-p 85. The divider according to Fabiano utilizes a latch disclosed in the same paper.
A 25% divider is in the art often called a 4-phase generator.
The divider and latch disclosed by Fabiano are derived from a circuit disclosed in an article by Behzad Razavi et al., “Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS”, IEEE journal of solid-state circuits, vol. 30, No. 2, February 1995. In the article several novel circuits are disclosed.
In general, there are potential timing problems associated with the latch circuit disclosed by Razavi. Even though the circuit operates properly in a specific application, the circuit poses timing uncertainty, i.e. in latch mode of operation there is a possibility of overriding the stored state in the circuit.